1. Field of the Invention
The present invention relates to memory control and the use of memories, especially in packet switched telecommunications networks and at nodes in such networks.
2. State of the Art
During scheduling of data transfer of a packet switched network a traffic manager needs to buffer quite a large amount of data to allow scheduling in case of heavy traffic and to equalize bursty traffic. Failure to do this can lead to dropping packets. Also, packets do not necessarily leave a node in the same order they arrive which also requires buffering.
The large amount of buffering needed at a packet switched network node can be solved by the use of cost-effective off-chip DRAM-based technology. Use of DRAM is associated with access latency. Regardless of technologies used to increase the bandwidth per pin (such as Double Data Rate (DDR) SDRAM or RAMBUS DRAM (RDRAM)), a main bottleneck in any DRAM implementation is the large bank turnaround time, which is currently around 60 ns. The bank turnaround time limits the frequency of accessing different (random) rows within a single bank, and therefore limits the data bus utilization drastically. For this reason, DRAM chips have multiple banks (typically 2 or 4) to increase the best-case bus usage, but this does not on its own change the worst-case bus usage.
A DRAM channel is defined as a single logical set of address (+ control) and data lines. A single channel has a particular width, which is the number of data lines and can be implemented using multiple DRAM components. A DRAM access cycle is defined as the sequence of operations performed on the address and data lines to do a particular random read or write request. The DRAM access cycle turnaround for a given amount of data is the time it takes between the start of either a random read or write request for that amount of data and the start of the next possible random read or write request. A DRAM bank is defined as a subset of a DRAM channel that has an independent access cycle. For example, if a channel has 4 banks, then up to 4 access cycles can be performed simultaneously. However, all banks within a particular channel share all address, control and data lines.
It is an object of the present invention to provide improved performance of a memory which is subject to access latency.
It is an object of the present invention to provide a memory structure having improved performance and for use in packet switched networks, especially in nodes of such a network.